The present disclosure generally relates to the field of integrated circuit design, and more particularly relates to design process technology co-optimization (DTCO).
Design space exploration has become a difficult problem due to the exponentially increasing size of design space of microprocessors and time-consuming simulations.
To address this issue, machine learning techniques have been widely employed to build predictive models. However, most previous approaches randomly sample the training set leading to considerable simulation cost and low prediction accuracy.
Design space exploration for DTCO is crucial for design rule development and failure mode analysis. Design space exploration is computationally expensive, especially when full factorial.
Current solutions and challenges are 1) generate all the critical patterns a design can think of; 2) run simulation on all generated patterns by Monte Carlo, and 3) find worst case scenarios based on simulation results.
Further the pattern coverage is limited by pattern complexity, generation, and storage. And the simulation is computationally expensive and does not scale well to high-dimensional design space.